1. Field of the Invention
The present invention relates generally to a system and method that allows page mode addressing to be retrofit to existing microprocessors that were designed without page mode addressing. More particularly, it relates to such a system and method that will predict central processing unit (CPU) memory accesses to addresses that can be accessed in a high speed mode. Most especially, it relates to such a system and method which does not require the use of higher speed hardware than other parts of the CPU and memory system. The invention further relates to a graphics display system incorporating a system and method for predicting CPU addresses.
2. Description of the Prior Art
Most data processing CPUs access memory in a sequential fashion. A sequential memory access in which the address of memory used for the access is either immediately above or immediately below the address of memory used in the preceding access.
Memory systems typically operate in both normal modes and high speed modes. Common high speed modes are page mode access and nibble mode access for ordinary dynamic random access memory (DRAM) and serial port access for dual port (Video RAM) memory systems. Since the high speed modes are typically twice as fast as the normal access mode, significant system performance improvements can be obtained if the high speed modes can be used for most accesses.
State of the art microprocessors typically incorporate CPUs with a type of sequential operation detector built into them. The fetching of instructions may require more than one memory access per instruction. These accesses are almost always sequential in nature. Previous sequential operation detectors used comparators of the current address and the previous address to detect sequentiality, or in some cases, inclusion in the same memory page. Such implementations require high speed hardware, usually higher speed than any other part of the CPU-memory system and can only be used on a CPU that provides the next address early enough in a cycle to allow for a decision soon enough for any actual system performance improvement. However, earlier microprocessor designs do not incorporate this sequential operation detection capability. If a way could be provided to retrofit this capability to existing microprocessor designs, the result would be a significant performance improvement with such microprocessors, while allowing use of the massive volumes of software and trained designers that are available for popular existing microprocessor designs.